AMD EPYC Integrated 9005: 8 to 192 ZEN-5 (c) Cores for Other Industry Segments 18 comments
In the Embedded 2025 world, AMD is bringing new EPYC processors that bring 8 to 192 Zen-5 (c) cores to other industry segments. As with previous generations, the most widespread agreement with standard models is sought; the EPYC Embedded 9005 is expected to begin shipping in the second quarter.
Embedded also represents long-term support. Instead of providing support for large EPYCs to date, AMD with the EPYC Integrated 9005, codenamed Turin, is now following the industry standard of at least seven years. The SP5 socket, which was already introduced with the predecessor EPYC (Embedded) 9004, codenamed Genoa, is still in use. With the new presentations, this is not likely to last more than a decade. Cisco and IBM will be the first companies to use AMD EPYC Embedded 9005 on a larger scale, AMD explains.
AMD EPYC Embedded 9005 ZUR Embedded World 2025
At first glance, the large server looks like a classic data center product. This is also the case in some regions, AMD said, although there are more diverse application areas that also include small single-slot systems or dual-core solutions fitted on appropriate boards.
Although the new contingent resembles many models that AMD already has in its portfolio, there are certainly adjustments. The variants with the highest clock are missing in the new integrated processors, but AMD does not do without the maximum number of cores. In an interview with TechAstuce from the integrated world 2025, the manufacturer explained that there is certainly a market for this, including in the storage environment or with large firewall support systems. According to the manufacturer, additional features that can quickly push data back and forth between DRAM and NVME SSDs in the event of a power failure between DRAM and NVME SSDS are only available in the AMDS integrated segment.
AMD EPYC Integrated 9005 (Bild: AMD)
AMD has confirmed that the models are suitable if a large customer requires it. However, the number of cores is not primarily changed, but the clock space is enlarged or reduced and the TDP is adapted to it, AMD said.
The basic equipment brings the EPYC processors via the SP5 platform known from the data center: up to 160 PCIe lanes, 12-channel memory with a maximum of 6,000 MT / s, possibly also in a size of up to 6 TB per socket.
Topics: AMD Embedded World 2025 EPYC Process Server Zen Source: AMD
Marc deciphers processors by testing their performance for gaming, content creation, and artificial intelligence.
