AMD Ryzen and Epyc with Zen 6(c): Rumors of Medusa Ridge, Point, Halo and Epyc “Venice”

and Epyc with Zen 6(c): Rumors about Medusa Ridge, Point, Halo and Epyc “Venice” 90 comments

AMD Ryzen and Epyc with Zen 6(c): Rumors about Medusa Ridge, Point, Halo and Epyc “Venice”

Zen 5 and Zen 5c for Ryzen 9000 (Granite Ridge, Strix Point, Strix Halo) and Epyc (Turin) are followed by Zen6 and Zen 6c – that and only that is officially known. However, since the spring there have been rumors of chipsets with up to 32 cores, and since the summer – code names. The author now provides more information.

New rumors about AMD Zen 6(c)

It is once again the Moore’s Law is Dead (MLID) YouTube channel which claims to have discovered new information about AMD’s Zen 6 generation. The channel, which spreads many rumors, undoubtedly has industry sources, but industry “leaks” are not considered particularly accurate. However, the X account Kepler_L2, known for its carefully published leaks, commented on the latest rumors with “Good Job”. The same account reported up to 32 cores per CCD in the spring.

MLID is probably now reporting new details about the Ryzen series Medusa Ridge (desktop Ryzen), Medusa Point (laptop with small iGPU) and Medusa Halo (based on Zen 6 (“Morpheus”) and Zen 6c (“Monarch” ). APU with large iGPU) and Venice (Epyc).

Current Zen 6 rumors, as reported by Moore's Law is Dead YouTube channel Current rumors about Zen 6, as spread by Moore’s Law is Dead YouTube channel (Image: MLID)

In the office with 12-core chipsets?

As a result, all three Medusa platforms are expected to share the same 12-core (3nm) CCD, which not only contradicts Kepler_L2’s prediction (Zen 6 with 8, 16, and 32-core chipsets), but should also that with Medusa, AMD is abandoning the monolithic (single die) approach it previously followed with APUs. But according to MLID, that’s exactly the case: In the future, the processor chipset and I/O chip will communicate via a new “low-latency base layer.” Like Strix Point, the iGPU should again be 16 CU wide. The NPU is “very large”.

Whether the chipset’s 12 cores are made up of 12 Zen 6s or a combination of Zen 6 and Zen 6c remains to be seen, but it’s most likely given Strix Point aka Ryzen AI 300 with Zen 5 and Zen 5c cores. However, MLID only explicitly talks about Zen 6.

Does Epyc 9006 increase Venice to 256 big cores?

For Venice aka Epyc 9006, MLID once again names a maximum of 8 chiplets with up to 32 Zen 6 cores and thus up to 256 cores – but from 2nm production. The fact that AMD separates Ryzen and Epyc in terms of chipset production would be new.

As “Turin Classic”, Turin aka Epyc currently a maximum of 128 Zen 5 cores with 16 8-core CCDs or a maximum of 192 Zen 5c cores with 12 16-core CCDs. Venice would again reduce the number of CCDs with Zen 6 CCDs four times wider – unless the rumor currently mixes the Zen 6 and Zen 6c variants.

Topics: AM5 AMD Ryzen Zen processors Source: X (Twitter)

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